1. Field of the Invention
Embodiments of the invention generally relate to sputtering processes, and more specifically, to sputtering processes for forming of metal interconnects in integrated circuits.
2. Description of the Related Art
Sputtering, alternatively called physical vapor deposition (PVD), is a prevalent method for depositing layers of metals and related materials in the fabrication of integrated circuits. Although originally sputtering was principally used to deposit substantially planar films for horizontal interconnects, more recent techniques have been developed to coat thin, conformal metal or metal nitride layers in holes formed within a dielectric layer. Such holes may be very narrow vias penetrating the dielectric layer which may be filled with a conductive material to provide vertical electrical interconnections between wiring layers.
Sputtering technology faces increasing challenges as the feature size of advanced integrated circuits continues to decrease. Sputtering is basically a process ill suited to coat the walls of high aspect-ratio holes. A typical via structure is illustrated in the cross-sectional view of FIG. 1. A lower dielectric layer 10 on a substrate 90 includes a conductive feature 12 formed within. An upper dielectric layer 14 is deposited over the lower dielectric layer 10 and conductive feature 12. A via hole 16 may be etched through the upper dielectric layer 14 overlying the conductive feature. In one example, the thickness of the dielectric layer 14 may be about 1 μm, while the width of the via hole 16 may be about 0.13 μm or less, such as about 65 nm. As a result, the via holes 16 have increasing aspect ratios, hence present some of the greatest challenges.
A barrier layer 18 may be deposited onto the sidewalls of the via hole 16 and on the planar field region on the top of the dielectric layer 14. The barrier layer 18 prevents diffusion between the dielectric layer 14 and metal which will be subsequently filled into the via hole 16. A metal seed layer 20 is then deposited on the barrier layer 18. The seed layer 20 may be composed of copper, tungsten, aluminum, ruthenium, or cobalt.
However, sputtering tends to create overhangs 28 in the seed layer 20 on the upper corner of the hole 16. Such overhangs 28 may introduce serious problems. The overhangs 28 progressively grow and narrow the passageway of the via hole 16 during the sputter deposition, thus effectively increasing the aspect ratio and further decreasing the sputter flux into the hole 16. Even for an electrochemical plating (ECP) fill, the overhangs 28 present an impediment to the flow of fresh electrolyte. In a worst case, the overhangs 28 can bridge and enclose the via hole 16 and prevent further deposition into the hole 16.
For the forgoing reasons, there is a need for improving the sputter deposition so as to prevent overhanging of the seed layer within the vias on a substrate surface.